The present invention relates to the control of data to a two-dimensional display screen, e.g., on a computer monitor. More particularly, the present invention is directed to a technique for providing a variable resolution display.
Computers commonly operate in different display modes with different display characteristics, in accordance with the requirements of the data being displayed. For example, a typical computer may operate its display in either a text or graphics mode, and may be capable of several different types of graphics modes. Bit plane graphics provides the least expensive way of displaying information on the screen, simply storing one bit for each pixel. However, the versatility of the display is not very good, since the allocation of only one bit per pixel means that no shading can be shown.
Gray scale level displays require more memory to store an image of the same resolution. E.g., by allocating four bits per pixel, each pixel can be shown in sixteen different levels of shading, thus increasing the versatility in what kinds of displays can be provided. For the same resolution, however, a gray level display with four bits per pixel will require a frame buffer which is four times as large as that required for a bit plane graphics display.
Finally, color displays typically allocate between four and eight bits per pixel to allow any given pixel to be represented in a large number of different color shades. To provide the same level of resolution as above, the frame buffer for a color display would necessarily be four to eight time larger than for a bit plane graphics system.
It would be desirable to provide a universal display controller capable of operating in each of the three different modes, but a number of problems are encountered. If the same spatial resolution is required for each different mode, the only approach would be to provide a frame buffer of maximum size which could provide high resolution images even in a color display having a "depth" of eight bits per pixel. Such an arrangement, however, would be expensive not only due to the cost and size of the frame buffer, but also as a result of the very high cost of high resolution color monitors as compared with gray level or black-and-white (B&W) monitors of the same resolution. As a practical matter, there is not often a requirement for equal resolution in both B&W and color modes. Moderately priced systems may include a high resolution B&W monitor and lower resolution color monitor. Higher priced systems may also utilize monitors with different resolutions, since B&W monitors in general provide higher resolution than the best color monitors. It is therefore desirable to provide a means for operating at different display resolutions.
Examples of display controllers adaptable to different resolutions are disclosed in U.S. Pat. Nos. 4,500,875 to Schmitz and 4,236,228 to Nagashima et al. The latter discloses a technique whereby a slow addressing method is used to assist the microprocessor in appropriately addressing a memory location, but this is not practical for providing fast video refresh. The former reference discloses a technique wherein a plurality of gates are provided in the video data path between the frame buffer and color map memory. This is disadvantageous not only due to the complexity of the gate array but also in that the different propagation paths through the gate array must be very short and of equal propagation delay, requiring further complex hardware to ensure satisfaction of the timing requirements.
A display controlling with a permanent frame buffer configuration requires a very large frame buffer size to handle both requirements of high resolution and of maximum pixel depth. It is possible to provide additional hardware to reconfigure the frame buffer structure for particular applications, but such additional hardware would be quite expensive.